Frequency synthesisers can be used to derive a stable high frequency signal from a lower frequency clock. An example of a known frequency synthesiser topology is schematically illustrated in FIG. 1.
The frequency synthesiser 1 comprises a master oscillator 2, which is typically a crystal oscillator, which defines a well controlled clock signal. An output of the oscillator 2 is provided either directly, or indirectly, to a first input 4 of a phase comparator 6. An output 8 of the phase comparator 6 is provided to an input of a voltage controlled oscillator 12 via a filter 10. The filter 10 is included so as to filter out unwanted noise.
An output of the voltage controlled oscillator is provided to an input of a dual modulus pre-scaler 20. The pre-scaler 20 is responsive to a pre-scaler control signal to divide by input signal by M or by N, which is typically M+1.
An output of the pre-scaler is provided to first and second counters 22 and 24, respectively. The person skilled in the art may know the counters as “A” and “B” counters.
The “A” counter 22 determines the number of voltage controlled oscillator cycles that the pre-scaler will divide by M+1. The action of dividing by M+1 is often known to the person skilled in the art as “swallowing cycles” as it is equivalent to dividing by M and “swallowing” (discarding) one cycle. The B counter merely counts the number of cycles output by the pre-scaler.
This arrangement allows the effective divide ratio of the divider formed by the pre-scaler and the first and second counters to assume any integer number.